MIPS

MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA) developed by MIPS Computer Systems, now MIPS Technologies, based in the United States. It is relevant for powering every SGI machine between the Professional IRIS and Tezro

Overview of MIPS

John Hennessy and his colleagues developed the Stanford MIPS (Microprocessor without Interlocked Pipeline Stages) project as one of the pioneering Reduced Instruction Set Computer (RISC) designs, the other being Berkeley RISC. MIPS Computer Systems was spun off in 1984 to commercialize the work, and SGI became one of its earliest and most influential customers.

SGI’s embrace of MIPS began in 1986 with the Professional IRIS series, powered by the R2000. This marked a shift away from Motorola 68k processors in SGI’s earlier IRIS Series workstations.

MIPS was continually refined over the relationship with SGI, culminating in the R12000 family and higher clock derivatives including the R14000 and R16000. SGI's financial troubles in the early 2000s led to them selling off the MIPS IP and eventually migrating to Itanium 2 architecture, which was being pushed as a joint HPE/Intel venture and similarly adopted by Compaq and several Japanese companies to replace older RISC designs.

The MIPS ISA

The MIPS architecture was designed from the outset to embody the principles of RISC: a streamlined instruction set, fixed instruction length, and a load/store architecture with all arithmetic performed on registers. SGI’s adoption of MIPS closely paralleled the evolution of the base instruction set, from the original MIPS I through to the more advanced MIPS IV. Each revision brought features that directly enabled the scaling of SGI’s workstations, graphics systems, and supercomputers.

MIPS I (1985)

• First implemented in: R2000, R3000
• Word size: 32-bit
• Registers: 32 general-purpose integer registers, 32 floating-point registers (coprocessor 1)
• Features: Simple 5-stage pipeline, branch delay slots, no unaligned memory accesses, no integer multiply/divide in the base pipeline (offloaded to optional coprocessor).

MIPS II (1990)

• First implemented in: R6000, later incorporated in the R4000
• Word size: 32-bit with extended support for larger address spaces
• Enhancements:
  • Improved exception handling model
  • More robust branch instructions
  • Additional atomic instructions for multiprocessor synchronization (load-linked/store-conditional, LL/SC)

MIPS III (1991)

• First implemented in: R4000
• Word size: 64-bit, but retaining 32-bit backward compatibility
• Enhancements:
  • 64-bit general-purpose and floating-point registers
  • 64-bit virtual addressing (with 32-bit compatibility mode)
  • Refinement of TLB-based virtual memory handling
• Impact on SGI: This ISA opened the door for SGI’s transition to 64-bit computing in the early 1990s. It underpinned the Indigo², Indy, and the first large-scale Origin servers, enabling much larger memory footprints and high-precision scientific workloads.

MIPS IV (1994)

• First implemented in: R8000 (T5), later in R10000
• Word size: 64-bit
• Enhancements:
  • Extended floating-point capabilities, including fused multiply-add (MADD/MSUB)
  • Support for quad-word (128-bit) floating-point operations
  • Conditional move instructions (eliminating some branches)
  • Expanded set of integer operations for high-performance code generation

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Although SGI’s processors were formally based on the MIPS I–IV ISAs, they were not fully binary compatible with the later MIPS32 and MIPS64 standards codified by MIPS Technologies for embedded use. SGI’s “R-series” processors added implementation-specific features, relied on instruction scheduling tuned for their deep pipelines, and assumed large secondary caches and system controllers. In practice, software compiled for MIPS III and IV systems will not run unmodified on a generic MIPS32/MIPS64 platform, and vice versa. This incompatibility stemmed from SGI’s emphasis on high-performance computing: their designs favored advanced floating-point operations, multiprocessor synchronization, and ccNUMA scalability, while embedded MIPS was optimized for code density, power efficiency, and broad compatibility across licensees.

MIPS Processor Timeline

CPU Name	Release Date	ISA Version	Derived from
R2000	1986	MIPS I	N/A
R3000	1988	MIPS I	R2000
R4000	1991	MIPS III	N/A
R4400	1993	MIPS III	R4000
R8000 (T5)	1994	MIPS IV	N/A
R10000	1996	MIPS IV	N/A
R12000	1998	MIPS IV	R10000
R14000	2001	MIPS IV	R12000
R16000	2002	MIPS IV	R14000
R16000A	2004	MIPS IV	R16000